RISC-V Instruction Set Reference

This document contains a brief listing of instructions and pseudocode for the RISC-V “I” (Integer) and “M” (Multiply-Divide) extensions. The RISC-V Assembler Reference contains information on programming in assembly language for RISC-V. For detailed information on the instruction set refer to the RISC-V ISA Specification. This project is a continuation of previous work by michaeljclark.

The following notation is used in the psuedocode:

Notation	Description
_pc	_{program counter}
_rd	_{integer register destination}
_rsN	_{integer register source N}
_imm	_{immediate operand value}
_offset	_{immediate program counter relative offset}
_ux(reg)	_{unsigned XLEN-bit integer (32-bit on RV32, 64-bit on RV64)}
_sx(reg)	_{signed XLEN-bit integer (32-bit on RV32, 64-bit on RV64)}
_uN(reg)	_{zero extended N-bit integer register value}
_sN(reg)	_{sign extended N-bit integer register value}
_{uN[reg + imm]}	_{unsigned N-bit memory reference}
_{sN[reg + imm]}	_{signed N-bit memory reference}

The following tables list the RISC-V RV32IM and RV64IM instructions.

RV32I Base Integer Instruction Set

Format	Name	Pseudocode
`_{LUI rd,imm}`	_{Load Upper Immediate}	_{rd ← imm}
`_{AUIPC rd,offset}`	_{Add Upper Immediate to PC}	_{rd ← pc + offset}
`_{JAL rd,offset}`	_{Jump and Link}	_{rd ← pc + length(inst) pc ← pc + offset}
`_{JALR rd,rs1,offset}`	_{Jump and Link Register}	_{rd ← pc + length(inst) pc ← (rs1 + offset) ∧ -2}
`_{BEQ rs1,rs2,offset}`	_{Branch Equal}	_{if rs1 = rs2 then pc ← pc + offset}
`_{BNE rs1,rs2,offset}`	_{Branch Not Equal}	_{if rs1 ≠ rs2 then pc ← pc + offset}
`_{BLT rs1,rs2,offset}`	_{Branch Less Than}	_{if rs1 < rs2 then pc ← pc + offset}
`_{BGE rs1,rs2,offset}`	_{Branch Greater than Equal}	_{if rs1 ≥ rs2 then pc ← pc + offset}
`_{BLTU rs1,rs2,offset}`	_{Branch Less Than Unsigned}	_{if rs1 < rs2 then pc ← pc + offset}
`_{BGEU rs1,rs2,offset}`	_{Branch Greater than Equal Unsigned}	_{if rs1 ≥ rs2 then pc ← pc + offset}
`_{LB rd,offset(rs1)}`	_{Load Byte}	_{rd ← s8[rs1 + offset]}
`_{LH rd,offset(rs1)}`	_{Load Half}	_{rd ← s16[rs1 + offset]}
`_{LW rd,offset(rs1)}`	_{Load Word}	_{rd ← s32[rs1 + offset]}
`_{LBU rd,offset(rs1)}`	_{Load Byte Unsigned}	_{rd ← u8[rs1 + offset]}
`_{LHU rd,offset(rs1)}`	_{Load Half Unsigned}	_{rd ← u16[rs1 + offset]}
`_{SB rs2,offset(rs1)}`	_{Store Byte}	_{u8[rs1 + offset] ← rs2}
`_{SH rs2,offset(rs1)}`	_{Store Half}	_{u16[rs1 + offset] ← rs2}
`_{SW rs2,offset(rs1)}`	_{Store Word}	_{u32[rs1 + offset] ← rs2}
`_{ADDI rd,rs1,imm}`	_{Add Immediate}	_{rd ← rs1 + sx(imm)}
`_{SLTI rd,rs1,imm}`	_{Set Less Than Immediate}	_{rd ← sx(rs1) < sx(imm)}
`_{SLTIU rd,rs1,imm}`	_{Set Less Than Immediate Unsigned}	_{rd ← ux(rs1) < ux(imm)}
`_{XORI rd,rs1,imm}`	_{Xor Immediate}	_{rd ← ux(rs1) ⊕ ux(imm)}
`_{ORI rd,rs1,imm}`	_{Or Immediate}	_{rd ← ux(rs1) ∨ ux(imm)}
`_{ANDI rd,rs1,imm}`	_{And Immediate}	_{rd ← ux(rs1) ∧ ux(imm)}
`_{SLLI rd,rs1,imm}`	_{Shift Left Logical Immediate}	_{rd ← ux(rs1) « ux(imm)}
`_{SRLI rd,rs1,imm}`	_{Shift Right Logical Immediate}	_{rd ← ux(rs1) » ux(imm)}
`_{SRAI rd,rs1,imm}`	_{Shift Right Arithmetic Immediate}	_{rd ← sx(rs1) » ux(imm)}
`_{ADD rd,rs1,rs2}`	_Add	_{rd ← sx(rs1) + sx(rs2)}
`_{SUB rd,rs1,rs2}`	_Subtract	_{rd ← sx(rs1) - sx(rs2)}
`_{SLL rd,rs1,rs2}`	_{Shift Left Logical}	_{rd ← ux(rs1) « rs2}
`_{SLT rd,rs1,rs2}`	_{Set Less Than}	_{rd ← sx(rs1) < sx(rs2)}
`_{SLTU rd,rs1,rs2}`	_{Set Less Than Unsigned}	_{rd ← ux(rs1) < ux(rs2)}
`_{XOR rd,rs1,rs2}`	_Xor	_{rd ← ux(rs1) ⊕ ux(rs2)}
`_{SRL rd,rs1,rs2}`	_{Shift Right Logical}	_{rd ← ux(rs1) » rs2}
`_{SRA rd,rs1,rs2}`	_{Shift Right Arithmetic}	_{rd ← sx(rs1) » rs2}
`_{OR rd,rs1,rs2}`	_Or	_{rd ← ux(rs1) ∨ ux(rs2)}
`_{AND rd,rs1,rs2}`	_And	_{rd ← ux(rs1) ∧ ux(rs2)}
`_{FENCE pred,succ}`	_Fence
`_FENCE.I`	_{Fence Instruction}

RV64I Base Integer Instruction Set (in addition to RV32I)

Format	Name	Pseudocode
`_{LWU rd,offset(rs1)}`	_{Load Word Unsigned}	_{rd ← u32[rs1 + offset]}
`_{LD rd,offset(rs1)}`	_{Load Double}	_{rd ← u64[rs1 + offset]}
`_{SD rs2,offset(rs1)}`	_{Store Double}	_{u64[rs1 + offset] ← rs2}
`_{SLLI rd,rs1,imm}`	_{Shift Left Logical Immediate}	_{rd ← ux(rs1) « sx(imm)}
`_{SRLI rd,rs1,imm}`	_{Shift Right Logical Immediate}	_{rd ← ux(rs1) » sx(imm)}
`_{SRAI rd,rs1,imm}`	_{Shift Right Arithmetic Immediate}	_{rd ← sx(rs1) » sx(imm)}
`_{ADDIW rd,rs1,imm}`	_{Add Immediate Word}	_{rd ← s32(rs1) + imm}
`_{SLLIW rd,rs1,imm}`	_{Shift Left Logical Immediate Word}	_{rd ← s32(u32(rs1) « imm)}
`_{SRLIW rd,rs1,imm}`	_{Shift Right Logical Immediate Word}	_{rd ← s32(u32(rs1) » imm)}
`_{SRAIW rd,rs1,imm}`	_{Shift Right Arithmetic Immediate Word}	_{rd ← s32(rs1) » imm}
`_{ADDW rd,rs1,rs2}`	_{Add Word}	_{rd ← s32(rs1) + s32(rs2)}
`_{SUBW rd,rs1,rs2}`	_{Subtract Word}	_{rd ← s32(rs1) - s32(rs2)}
`_{SLLW rd,rs1,rs2}`	_{Shift Left Logical Word}	_{rd ← s32(u32(rs1) « rs2)}
`_{SRLW rd,rs1,rs2}`	_{Shift Right Logical Word}	_{rd ← s32(u32(rs1) » rs2)}
`_{SRAW rd,rs1,rs2}`	_{Shift Right Arithmetic Word}	_{rd ← s32(rs1) » rs2}

RV32M Standard Extension for Integer Multiply and Divide

Format	Name	Pseudocode
`_{MUL rd,rs1,rs2}`	_Multiply	_{rd ← ux(rs1) × ux(rs2)}
`_{MULH rd,rs1,rs2}`	_{Multiply High Signed Signed}	_{rd ← (sx(rs1) × sx(rs2)) » xlen}
`_{MULHSU rd,rs1,rs2}`	_{Multiply High Signed Unsigned}	_{rd ← (sx(rs1) × ux(rs2)) » xlen}
`_{MULHU rd,rs1,rs2}`	_{Multiply High Unsigned Unsigned}	_{rd ← (ux(rs1) × ux(rs2)) » xlen}
`_{DIV rd,rs1,rs2}`	_{Divide Signed}	_{rd ← sx(rs1) ÷ sx(rs2)}
`_{DIVU rd,rs1,rs2}`	_{Divide Unsigned}	_{rd ← ux(rs1) ÷ ux(rs2)}
`_{REM rd,rs1,rs2}`	_{Remainder Signed}	_{rd ← sx(rs1) mod sx(rs2)}
`_{REMU rd,rs1,rs2}`	_{Remainder Unsigned}	_{rd ← ux(rs1) mod ux(rs2)}

RV64M Standard Extension for Integer Multiply and Divide (in addition to RV32M)

Format	Name	Pseudocode
`_{MULW rd,rs1,rs2}`	_{Multiple Word}	_{rd ← u32(rs1) × u32(rs2)}
`_{DIVW rd,rs1,rs2}`	_{Divide Signed Word}	_{rd ← s32(rs1) ÷ s32(rs2)}
`_{DIVUW rd,rs1,rs2}`	_{Divide Unsigned Word}	_{rd ← u32(rs1) ÷ u32(rs2)}
`_{REMW rd,rs1,rs2}`	_{Remainder Signed Word}	_{rd ← s32(rs1) mod s32(rs2)}
`_{REMUW rd,rs1,rs2}`	_{Remainder Unsigned Word}	_{rd ← u32(rs1) mod u32(rs2)}

References

This project is a continuation of previous work by michaeljclark.

RISC-V Guide

RISC-V ISA Reference